1. Field of the Invention
The present invention relates to a chip package and a fabrication method therefor, and in particular, to an improved Ball Grid Array (BGA) package a fabrication method therefor.
2. Background of the Related Art
BGA packages are widely used since they make it possible to implement a multiple pin structure in a limited surface area. In addition, since the outer terminals of the BGA package are short, the terminals and package are less likely to be bent due to an externally applied force or impact. Furthermore, it is possible to easily transmit electrical signals in the BGA package. Also, when mounting the package on a mother board, it is possible to reduce the mounting time for the package by using a reflow mounting method which is performed in a furnace for a short time.
FIG. 1 illustrates a related BGA package. As shown therein, the BGA package includes a substrate 1, a semiconductor chip 3 mounted on the upper surface of the substrate 1 by an adhesive 2, metal wires 4 electrically interconnection a plurality of chip pads 3a formed on the upper surface of the chip 3 with circuit patterns (not shown) formed on the substrate 1, a molding section 5 formed on the upper surface of the substrate 1 and encapsulating the chip 3 and metal wires 4, and a plurality of solder balls 6 attached on the lower surface of the substrate 1.
To fabricate the package, the semiconductor chip 3 is attached to the upper central portion of the substrate 1 by the adhesive 2 in a die bonding process. Thereafter, in a wire bonding process, the chip pads 3a formed on the upper surface of the semiconductor chip 3 and the patters (not shown) formed on the substrate 1 are interconnected with the metal wires 4. In a molding process, the semiconductor chip 3, the metal wires 4, and a portion of the upper surface of the substrate 1 are encapsulated with epoxy, thus forming the molding section 5. In a solder ball attaching process, the solder balls 6 are attached to the lower surface of the substrate 1.
However, in he related BGA package, the substrate 1 requires a predetermined upper surface are and thickness. Further, the metal wires 4 must have a predetermined length to accommodate the height of a loop. Accordingly, it is not possible to fabricate a lighter and more compact package. In addition, the wire bonding process of interconnecting the chip pads 3a and the patterns (not shown) on the substrate 1 is very difficult to perform, and requires a significant amount of time. Accordingly, there is a limit to the productivity that can be achieved when making this type of BGA package.